Product Summary

The XC1701PD8C is a Configuration PROM. It provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. The XC1701PD8C is compatible and can be cascaded with other members of the family. The FPGA generates the appropriate number of clock pulses to complete the configuration. After configured, it disables the XC1701PD8C. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal.

Parametrics

XC1701PD8C absolute maximum ratings: (1)Supply voltage relative to GND:–0.5 to +7.0V; (2)Supply voltage relative to GND:–0.5 to +12.5 ; (3)Input voltage relative to GND:–0.5 to VCC +0.5V; (4)Voltage applied to High-Z output:–0.5 to VCC +0.5V; (5)Storage temperature (ambient):–65 to +150℃; (6)Junction temperature:+125℃.

Features

XC1701PD8C features: (1)One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGAs; (2)Simple interface to the FPGA; requires only one user I/O pin; (3)Cascadable for storing longer or multiple bitstreams; (4)Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions ; (5)Low-power CMOS floating-gate process; (6)Available in compact plastic packages: 8-pin SOIC, 8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-pin PLCC or 44-pin VQFP; (7)Programming support by leading programmer manufacturers; (8)Design support using the Xilinx Alliance and Foundation software packages; (9)Guaranteed 20 year life data retention; (10)Lead-free (Pb-free) packaging available.

Diagrams

XC1701PD8C block diagram

XC1700D
XC1700D

Other


Data Sheet

Negotiable 
XC1700E
XC1700E

Other


Data Sheet

Negotiable 
XC1700L
XC1700L

Other


Data Sheet

Negotiable 
XC1701
XC1701

Other


Data Sheet

Negotiable 
XC1701L
XC1701L

Other


Data Sheet

Negotiable 
XC1701PC20C
XC1701PC20C


IC PROM SER C-TEMP 1K 20-PLCC

Data Sheet

Negotiable